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Model 501V 32Mbps VME Bit Synchronizer

Product Support

 

  • Tunable from 8bps to 32Mbps (NRZ codes) and 16 Mbps (all others)

  • Processes all IRIG standard and randomized codes

  • Independent PCM encoder with both internal and external clock/data inputs

  • Fast sync acquisition - less than 32 bits, typical

  • Excellent BER performance, 1dB or better

  • Direct decoding/encoding of TTL or RS422 clock/data sources

  • Frame Synchronizer with auto-polarity and automated data source selector

  • Full featured BERT with "live” data BER monitor

  • Field upgradeable options module for future expansion

 

Technical Manual

Program & User's Manual

Datasheet

Technical Specs

Software & Drivers

Overview

 

The 501V PCM Bit Synchronizer is a state of the art bit synchronizer featuring tunable data rates from 8Hz to 32MHz for NRZ codes and to 16MHz for others.    

The 501V is suppiled with the Model  2220V or Model 2222V  Telemetry Data Processor (Maximum 8), the Model 2440V Multi Bit Sync Chassis (Maximum 16) and the Model 2430V Bit Synchronizer (Maximum 2).  A common software GUI can control these cards, independent of the chassis.

The Model 501V can be enhanced with a programmable logic module. Current options include Viterbi Decoding, a frame simulator/synchronizer and a built-in bit error rate test (BERT) generater/receiver. The logic module is reprogrammable and can be replaced in the field without any special tools, thus, minimizing down time when an upgrade becomes necessary. These unique capabilities allow you to respond quickly to evolving application requirements such as:

• Recovering data from newly defined or application specific coding schemes

• Creating canned formats for recovering data from concatenated or layered codes

• Monitoring data streams for frame synchronization to resolve ambiguities or polarity inversions typical with many  modulation schemes

 

 

System Software

 

GUI Setup and Operation Status for the 501V is controlled via a single interface with drop down menus for individual cards. The software automatically recognizes all of the bit synchronizers as well as their features. Setup configurations can be stored and retrieved for all previous missions as a group or individually. A page lock command accessible via the GUI reminds users before executing new instructions in order to avoid mistakes during a live mission. Remote users can control the units via an Ethernet port. If two users are viewing the system simultaneously, both see the changes made in real time by either user.

Technical Specs

SYSTEM FUNCTIONS

Acroamatics Bit Synchronizer Software

Included

GUI Interface

Standard

Operating System

Windows 2000/XP

Special Features

Lock out per bit sync, Auto-sensing configuration, Setups stored per system or mission, Remote bit synchronizer  GUI Display via Ethernet

SIGNAL INPUTS

Source

Program selectable: one of four inputs

Isolation

Greater than 60dB at 32Mhz

Impedance

Program selectable: Hi-Z/Lo-Z. Single Ended: 10kΩ/75Ω, Differential: 10kΩ/120Ω

Signal Level

Single Ended: 0.2 to 30V p-p, Differential: 0.2 to 25V p-p

DC Offset

20V max Single-Ended, Hi-Z

Baseline Variation

 Tracks sinusoidal offsets to 100% p-p signal amplitude at 0.1% bit rate

PCM Codes

 Program selectable: NRZ-L/M/S, Biø-L/M/S, DBiø-M/S, DM-M/S, MDM-M/S, RZ

Derandomizer

 Program selectable: RNRZ 9/11/15/17/23, forward/reverse

SYNCHRONIZATION

Bit Rate Range

8bps-32Mbps NRZ codes, 8bps-16Mbps all others

Tuning Resolution

0.1% of bit rate

Capture Range

3 times the programmed loopwidth, typical

Tracking Range

±12% typical, with programmable limiter

Loop Bandwidth

0.1% to 3.2%, program selectable in 0.1% increments

Sync Threshold

0dB for NRZ-L and Biø-L codes

Sync Maintenance

 (LW=0.1%) –2dB NRZ-L and Biø-L codes

Sync Acquisition

 (LW=1.6%, SNR > 12dB) Typically less than 32 bit periods

Sync Retention

(LW=0.1%, SNR > 3dB) Retains sync through > 128 consecutive dropouts

Bit Error Rate

(LW=0.1%) to within 1dB of ideal bit error rate performance curves

DATA/CLOCK OUTPUTS (TAPE & CODE OUTPUTS)

NRZ-L Data

Three TTL, one RS422/TTL

Data Clock

Two program selectable TTL: 0º, 90º, 180º, 270º

Quadrature Clocks

 One each: 0º, 90º, 180º, 270º; RS422/TTL

2x Clock

One TTL, One RS422/TTL

Data Polarity

Program selectable: normal/inverted

SOFT BIT DECISION OUTPUT

Data/clock

Three bits Offset Binary plus 0º clock; TTL (open collector)

Sample Rate

Programmable to 32 megasamples per second

PCM ENCODER

Data Source

Program selectable: Recovered Data or External data, or Test generator

Outputs

One bipolar, 4V p-p; Two TTL; One RS422/TTL

Randomizer

Program selectable: RNRZ 9/11/15/17/23

PCM Codes

Program selectable: NRZ-L/M/S, Biø-L/M/S, DBiø-M/S, DM-M/S, MDM-M/S, RZ

EXTERNAL DATA/CLOCK INPUT

Signal Type

Selectable: RS422 or TTL

Impedance

120Ω RS422, 75Ω TTL

Data Code

Program selectable: NRZ-L/M/S, Biø-L/M/S, DBiø-M/S, DM-M/S, MDM-M/S, RZ

Data Clock

Program selectable: Normal/Inverted, 1x or 2x

CONVOLUTIONAL ENCODER/DECODER (OPTIONAL)

Viterbi Decoder

Rate 1/2, k=7: includes differential decoding, V.35 descrambling, and G2 invert

Symbol Formats

serial, parallel, and staggered parallel

Convolutional Encoder

Rate 1/2, k=7: includes differential encoder, V.35 scrambler, and G2 inverter

Symbol Formats

serial, parallel, and staggered parallel

FORMAT GENERATOR/SYNCHRONIZER  (OPTIONAL)

Format Generator

Programmable frame length, sync pattern and mask

Synchronizer Source

Program selectable: Recovered data, external data, or Test generator

Synchronizer Strategy

Pattern match in "search", programmable error limits for "check" and "lock" states

Other Features

Bit slip enable, auto polarity enable, data source/ambiguity resolution

BIT ERROR RATE TESTER (OPTIONAL)

Transmitter Pattern

PRN sequence: 27-1, 29-1, 211-1, 215-1 (forward/reverse)

Pattern Generator Clock

Selectable: Clock, External Clock or Programmable Clock 1bps to 40Mbps

Blanking

Program selectable: 32, 64, 128 bits -synchronized to BER counter

BER Sample Period

Program selectable: 103 to 109 bit periods, or continuous accumulate

Other Features

Automatic pattern synchronization, forced error ON/OFF, Tape out attentuator

PHYSICAL

Format

Single Slot  6U VME

Cooling Requirements

30 Linear FPM

Power Requirements

+5VDC at 1.25 Amp, +12VDC at 800mA, -12VDC at 500mA

Temperature

Operating 0 to +40°C, non-operating –40 to +86°C

Relative Humidity

Up to 90% non-condensing

Shock

Operating 6G, Non-operating 50G

Vibration

Operating 0.5G, 5 to 2000Hz, Non-Operating 1.2G, 5 to 500Hz

specifications subject to change without notice

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