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Model 1650P Frame Sync Verification Unit

Product Support

  • 8 - 32 Mbps

  • Eight Channel

  • Automatic Polarity Inversion

  • Optional Time Code Translator/Generator

 

Technical Manual

Program Manual

Technical Specs

Software & Drivers

Datasheet

Supplemental System Products

470M Time Code Translator/Generator

Overview

 

The Model PCI 650 FSVU (Frame Synchronization Verification Unit) contains eight PCM Decommutators that are designed for PCM stream quality verification rather than data processing. Each decommutator contains a minor frame synchronizer with a 64 bit pattern correlator, a 16 bit counter that counts the number of bits per frame, and a programmable synchronizer strategy providing Search, Verify, and Lock states. A programmable watchdog timer returns a decommutator to Search if the input clock is lost. You can read the status of each of the eight decommutators over the PCI bus to determine the quality of the input data to each channel.

 

Technical Specs

INPUT

Sources

Eight channels, each accepting RS-422 differential 0 clock & NRZ data

Impedance

120Ω input impedance, TTL compatible

Bit Rate

Up to 32 Megabits per second

Polarity

Programmable, with automatic polarity correction

Frame Length

 Programmable, 16 to 16384 bits

SYNCHRONIZATION

Mainframe Sync

Provides for programmable sync pattern and mask, complement pattern recognition, and variable length frame decommutation. Pattern length up to 64 bits.

Alternate Complement Sync

Synchronizes to formats in which the minor frame sync pattern is complemented on alternate frames

Complement Frame Sync

Synchronizes to formats that complement the minor frame sync pattern at a major frame rate

Automatic Polarity Inversion

Input polarity is inverted when two consecutive complemented sync patterns are found.

Sync Modes

Fixed, Adaptive, and Burst

Sync Strategy

Search, Verify, and Lock

Sync Error Tolerance

0 to 15 errors, programmable

Sync Slip Window

0, 1, 2, & 3 bits, programmable

Data Polarity

 Normal, Inverted, and Automatic detection

Clock Rate Monitor

A programmable delay counter is provided to return the synchronizer to Search if the clock input is lost.

OUTPUT

Time

The Time Code Translator can be read from the PCI bus.

PCM Status

A status word is available for each PCM frame synchronizer via the PCI bus.

Discrete Status

The Lock status of each frame synchronizer is output as an RS-422 signal.

Serial Setup Output

A serial RS-422 output allows you to send data from the PCM bus to an external device.

CVT

 128k x 32 bit CVT memory, addressed by assigned PCM word ID tag. Read by the PCI bus, it contains last value from up to 128k TM sources.

Block Buffer Memory

Used to format and input up to 512k messages of 32 bit words. Six programmable formats: 4 with ID tags and 2 data only. May include programmable time stamp and header message.

DMA

Dual buffered DMA channel for transferring messages formatted for the block buffer memory directly to Host memory.

Mezzanine Card

A mezzanine connector supports an optional Time Code Translator/Generator (with or without PCM/PAM Simulator), The mezzanine card provides the following signals:

IRIG B In

Amplitude modulated IRIG A, B, or G with 100mV to 10 V peak to peak signal input amplitude. Simulator output is RS-422 NRZ-L data and 0 clock.

PHYSICAL

Format

Standard PCI: Half length single slot

Cooling Requirements

30 Linear FPM

Power Requirements

+5VDC at 1A, +3.3VDC at 2A

Dimensions

4.20" (10.67cm) H x 7.85" (19.94cm) W x .50" (1.27cm) D

Temperature

Operating 0 to +40C, non-operating 40 to +86C

Relative Humidity

Up to 90% non-condensing

Shock

Operating 6G, Non-operating 25G

Vibration

Operating 0.5G, 5 to 2000Hz, Non-Operating 1.2G, 5 to 500Hz

specifications subject to change without notice

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