Quick Product Link   


Model 1626P Multi-Channel PCM Quick-Look Processor

Product Support



IRIG A, B & G Time Code Translator for Time & Status stamping.


64MHz PCM Format Simulator for testing and checkout.


Serial PCM Record / Playback Capability


NEW low-latency IRIG Ch 5 onboard CVSD and PCM encoded Digital Voice processing / reproduction


  • PCM bit rates to 64MHz

  • One to four independent Frame Syncs

  • Onboard IRIG Time Code Reader

  • Onboard 0 - 64 Mbps PCM Simulator

  • Accepts Model 474DM Bit Sync "daughter" mezzanine card

  • NEW IRIG Chapter 5 CVSD option

  • Optimized for data recording and post-processing applications

  • Individually programmable word properties

  • Minor frame lengths up to 64k words

  • Variable frame lengths

  • Programmable serializer extracts embedded data

  • Auto-double-buffering memory with 512kbyte per stream

  • 2 DMA channels

  • Direct PCI-bus data access


Technical Manual

Software Manual


Technical Specs

Software & Drivers



The Model 1626P is a single card "quick-look" PCM Processing card  (PCI Multi-Channel Frame Synchronizer) which can be ordered with from one to four PCM Frame Sync / Decommutators, each of which are optimized for PCM stream quality validation and quick-look data processing.  The 1626P includes an onboard Time Code Translator, programmable PCM Simulator, and accommodates Acroamatics optional "plug-on" Model 474DM tunable 40 MHz Advanced Digital Bit Synchronizer mezzanine module.


The model 1626P also offers a low-latency onboard CVSD voice processor option, with scalable D/A output, as an option.


Each 1626P onboard decommutator contains a powerful minor frame synchronizer with a 64 bit pattern correlator. The correlator provides programmable pattern, mask, and error tolerance thresholds. Frame synchronization is acquired and maintained with a programmable synchronizer strategy that processes SEARCH, VERIFY, and LOCK states. A programmable watchdog timer returns the decommutator to SEARCH if the input clock is lost. The status of each of the four decommutators can be read over the PCI bus to determine the quality of the input data to each channel. Data, time, and status messages can be stored into a block buffer memory that provides 32-bit messages for each channel.


The messages can be single frames, or generated to the length specified in the corresponding record length register. After the channel block buffer is complete the host processor can read flags or use an interrupt to sense if the data is ready for transfer. The host computer can read any data message directly from the PCI bus, or transfer the record via either of the two DMA channels provided on the PLX interface chip.



Technical Specs




Up to 4 channels - each accepts NRZ L/S RS-422 or NRZ L/S TTL.


RS-422: 120 Ω input impedance, TTL  50Ω input  impedance

Bit Rate

Up to 64 Megabits per second

Clock Polarity

Programmable 0 or 180

Data Polarity

Programmable, with automatic polarity correction

Frame Length

Programmable, 4 to 65536 words



Mainframe Sync

Provides for programmable sync pattern and mask, complement pattern recognition, and variable length frame decommutation. Pattern length up to 64 bits.

Alternate Complement Sync

Synchs to formats where the minor frame sync pattern complements on alternate frames

Complement Frame Sync

Synchs to formats that complement the minor frame sync pattern at a major frame rate

Automatic Polarity Inversion

Input polarity is inverted when two consecutive complemented sync patterns are found

Sync Modes

Fixed, Adaptive, and Burst

Sync Strategy


Sync Error Tolerance

0 to 15 errors, programmable

Sync Slip Window

0, 1, 2, & 3 bits, programmable

Clock Rate Monitor

A delay counter returns the synchronizer to SEARCH if the clock input is lost


The PCM format is decommutated by using the contents of the WORD PROPERTIES MEMORY (which provides one word

for each PCM word and one segment for each channel synchronizer) to decommutate the serial data into words. The

memory provides the following information for EACH WORD of the frame.


Bits in this word (from 1 to 32); the orientation of the input data, MSB or LSB first; if data

is right- or left-justified in the output word.

Serializer Enable

Enables the current word to be serialized to extract embedded data.

Suppress Bit

Setting this bit discards the current word from the output record.

Variable Length Frame

Setting this bit accepts the sync pattern at any position of the current word.

End Of Frame

Setting this flag recycles the frame at the completion of the current word.



Output Buffer Size

Double buffered 65,536 32-bit words, for each channel. Data may be read directly from

the PCI bus or via the DMA channels.


May be inserted at the start of each frame. Header components, Time, Status and Frame

number are user selectable.


Time of day in BCD microseconds, as a 64-bit word. If enabled, the time of day will

occupy the first two words of a 32-bit output format header.

Minor Frame Counter & Frame Status Word

16 bit sync status and the 16 bit free-running frame count is packed in a 32-bit output

word. The status message reflects hardware status at the first word of the frame is left-justified in the resulting 32 bit word.

Output Format

Data only, No ID tags, and all output words are 32 bits

Output Word Formatting

& Justification


16 or 32 bit word selection determines output word formation. The 16 bit format can be used when all PCM words are 16 bits or less. The 16 bit word format packs two right- or

left-justified 16 bit words into a 32 bit word. In 32-bit format the PCM words will be right or

left-justified into a 32 bit word.

Host PCM Status

A status word is available for each PCM frame synchronizer via the PCI bus.

Discrete Status

The LOCK status of each frame synchronizer can be outputted as an RS-422 signal.

Frame Mark

A frame mark can be outputted as an RS-422 signal.


The Time Code Translator can be read from the PCI bus, and The PARALLEL TIME word

may be included in each PCM frame.


A programmable PCM Simulator is provided to allow self tests & frame verification.

CVSD Voice

A programmable IRIG Chapter 5 compliant low-latency voice decoder & D-to-A output option is available.



Standard PCI: 3/4 length single slot

Cooling Requirements

30 Linear FPM

Power Requirements

+5.0 & 3.3VDC @ 600mA max each, 12 VDC @ 20 & 5 mA max respectively


4.20" (10.67cm) H x 7.85" (19.94cm) W x .50" (1.27cm) D


Operating 0 to +40C, non-operating 40 to +86C

Relative Humidity

Up to 90% non-condensing


Operating 6G, Non-operating 50G


Operating 0.5G, 5 to 2000Hz, Non-Operating 1.2G, 5 to 500Hz

specifications subject to change without notice

Request additional product information

2010 Acroamatics Inc. All rights reserved.