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Model 1601P 32Mbps Bit Synchronizer

Product Support


  • Tunable from 8bps to 32 Mbps (NRZ codes) and 10 Mbps (all others)

  • Processes all IRIG standard and randomized codes

  • Independent PCM encoders with both internal and external clock/data inputs

  • Viterbi, BERT, Ambiguity Resolution

  • Fast sync acquisition - less than 32 bits, typical

  • Excellent BER performance, 1dB or better

  • Direct decoding/encoding of TTL and RS422 clock/data sources

  • Frame Synchronizer with auto-polarity and automated data source selector

  • Full featured BERT with "live” data BER monitor

  • Field upgradeable options module for future expansion


Technical Manual

Program Manual


Technical Specs

Software & Drivers

Supplemental System Products

472M Bit Sync Mezzanine



32MHz PCM Bit Synchronizer on a single PCI card - mounts Acroamatics 472M Mezzanine Bit Synchronizer to provide two bit synchronizers in a single PCI slot.




The 1601P Bit Synchronizer is a state-of-the-art Bit Synchronizer featuring tunable data rates from 8 Hz to 32 MHz for NRZ codes and 8 Hz to 16 MHz for all others. The 1601P processes all IRIG standard and randomized codes and has a bit error performance within 1 dB of theoretical. Optional features include: Viterbi encoding/decoding, full featured BERT monitoring & frame synchronizer. The 1601P can also support an optional 472M Bit Synchronizer mezzanine giving you an additional Bit Synchronizer without occupying another PCI slot.  The 1601P comes with our standard GUI interface, cabling and user manual. All Acroamatics documentation is supplied on CD-ROM.


System Software


GUI Setup and Operation Status of the Model 1601P's and 472M's are controlled via a single interface with drop down menus for individual cards. The software automatically recognizes all of the bit synchronizers as well as their features. Setup configurations can be stored and retrieved for all previous missions as a group or individually. A page lock command accessible via the GUI reminds users before executing new instructions in order to avoid mistakes during a live mission. Remote users can control the units via an Ethernet port. If two users are viewing the system simultaneously, both see the changes made in real time by either user.

Technical Specs



Program select, 1 of 5 inputs: 3 single-ended, 1 differential, 1 TTL/RS-422


Greater than 60dB at 32MHz


Program selectable: Hi-Z/Lo-Z. Single Ended: 4kΩ/75Ω, Differential: 10kΩ/150Ω

Signal Level

Single Ended: 0.2 to 30V p-p, Differential: 0.2 to 25V p-p

DC Offset

20V max Single-Ended, Hi-Z

Baseline Variation

 Tracks sinusoidal offsets to 100% p-p signal amplitude at 0.1% bit rate

PCM Codes

 Program selectable: NRZ-L/M/S, Biø-L/M/S, DBiø-M/S, DM-M/S, MDM-M/S, RZ


 Program selectable: RNRZ 9/11/15/17/23, forward/reverse


Bit Rate Range

8bps-32Mbps NRZ , 8bps-16Mbps all others

Tuning Resolution

0.1% of bit rate

Capture Range

3 times the programmed loopwidth, typical

Tracking Range

±12% typical, with programmable limiter

Loop Bandwidth

0.1% to 3.2%, program selectable in 0.1% increments

Sync Threshold

0dB for NRZ-L and Biø-L codes

Sync Maintenance

(LW=0.1%) –2dB NRZ-L and Biø-L codes

Sync Acquisition

(LW=1.6%, SNR > 12dB) Typically less than 32 bit periods

Sync Retention

(LW=0.1%, SNR > 3dB) Retains sync through > 128 consecutive dropouts

Bit Error Rate

(LW=0.1%) to within 1dB of ideal bit error rate performance curves


NRZ-L Data

Jumper Select: three TTL, one RS422/TTL

Data Clock

One each: 0º, 90º, 180º, 270º; RS422/TTL at 0º & 90º

Data Polarity

Program selectable: normal/inverted


Data Source

Program selectable: Recovered Data or External data/clock


±2 Volts balanced output, 50mA drive current


Program selectable: RNRZ 9/11/15/17/23, forward, reverse

PCM Codes

Program selectable: NRZ-L/M/S, Biø-L/M/S, DBiø-M/S, DM-M/S, MDM-M/S, RZ


Signal Type

Jumper selectable: RS422 or TTL


120Ω RS422, 75Ω TTL

Data Code

Program selectable: NRZ-L/M/S, Biø-L/M/S, DBiø-M/S, DM-M/S, MDM-M/S, RZ

Data Clock

Program selectable: Normal/Inverted, 1x or 2x


Viterbi Decoder

Rate 1/2, k=7: includes differential decoding, V.35 descrambling, and G2 invert

Symbol Formats

serial, parallel, and staggered parallel

Convolutional Encoder

Rate 1/2, k=7: includes differential encoder, V.35 scrambler, and G2 inverter

Symbol Formats

serial, parallel, and staggered parallel


Format Generator

Programmable frame length, sync pattern and mask

Synchronizer Source

Recovered data, external data, or test generator

Synchronizer Strategy

Pattern match in "search", programmable error limits for "check" and "lock" states

Other Features

Bit slip enable, auto polarity enable, data source/ambiguity resolution


Transmitter Pattern

PRN sequence: 211-1, 27-1, 29-1, 215-1 (forward/reverse)

Pattern Clock Source

Program selectable: Bit Rate Clock or External Clock


Program selectable: 32, 64, 128 bits

BER Sample Period

Program selectable: 103 to 109 bit periods, or continuous accumulate

Other Features

Automatic pattern synchronization, forced error ON/OFF




Standard PCI: Full length single slot

Cooling Requirements

30 Linear FPM

Power Requirements

+3.3VDC @ 1.5A, +5VDC @ 1.0A, ±12VDC if 472M attached

Power Requirements 5 Volt version

+5VDC @ 3A, ±12VDC @ 150mA


4.20" (10.67cm) H x 12.5" (31.75cm) W x .55" (1.4cm) D


Operating 0 to +40°C, non-operating –40 to +86°C

Relative Humidity

Up to 90% non-condensing


Operating 6G, Non-operating 25G


Operating .3G, 5 to 2000 Hz, Non-operating .8G, 5 to 500 Hz

specifications subject to change without notice

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