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Model 1502V VME Single Board Data System

Product Support

 

  • Processes PCM streams to 32 MHz

  • Enlarged stored program space

  • 32-bit instruction words

  • Non-Segmented programs

  • 16 program flow control flags

  • Chapter 8 decommutation

  • Decommutates packeted TM

  • Current value table

  • Stream DMA

  • Programmable output formatting

  • Plug-on modules

    Bit Synchronizer

    IRIG Time Translator/Generator

    Format Simulator

Technical Manual

Program Manual

Datasheet

Technical Specs

Software & Drivers

Supplemental System Products

472M Bit Sync Mezzanine

470M Time/Sim Mezz

Overview

 

A VME single-board PCM data system that can operate independently in any VMEbus chassis, or replace the 502VA Format Synchronizer to bring the 1502V's advanced features to your Acroamatics TDP

Today's vehicle test operations produce more types and greater volumes of data and transmit it at higher rates and in increasingly complex formats - formats that change in both content and structure. The new Acroamatics programmable single-board PCM decommutator has the processing power and the large working memory to provide the flexibility to decommutate today's and tomorrow's high-speed, dynamically changing PCM formats. And its on-board time, bit synchronizer, and format simulator options make it a one-board PCM telemetry data system, freeing up slots for other uses.

 

The Model 1502V  decommutates complex PCM telemetry data streams at rates to 32 MHz.  The unit frame synchronizes and decommutates PCM formats with embedded asynchronous frames, variable length frames, and multiple sub-frame structures. The 1502V supports a variety of sub-frame sync pattern recognition methods, including fixed recycle patterns, syllabilized data patterns, JAM ID patterns, counting ID patterns, and alternating complement sync patterns. The 1502V decommutates formats with up to six independent sub-commutation structures. The card accepts input words of variable length, MSB or LSB oriented, with or without parity. A programmable Search-Check-Lock strategy, bit error tolerances, and bit slip windows provide reliable frame decommutation. The Model 1502V decommutates serial bit streams into data messages for downstream analysis. The Current Value Table supports real-time display of decommutated PCM data.

 

How it works

 

The 1502V Decommutator treats PCM data as a stream of bits divided arbitrarily into packets, each packet representing data values varying in length from 1 to 32 bits. The decommutator uses PCM stream sync patterns to identify the stream data sequence, then tags each packet sequence with a unique ID, regardless of location. The front end of the decommutator

is a pattern correlator that first locates the minor frame sync pattern, then generates control signals to activate a tracking computer operating in sync with the data stream. You program this computer with instructions designed to map a particular PCM format. This map tells the computer how to dissect and identify the serial data sequences forming the PCM stream. You can select the number of bits to extract from the stream for each packet individually, the LSB/MSB data orientation, the output

word MSB/LSB data justification, and how to handle a parity bit. You also assign the ID tag. The decommutator uniquely tags each measurement according to these instructions and outputs a data message containing your ID tag and the stream data. Adding a time tag to this message produces what Acroamatics calls a DIT (Data, ID, Time). Program instructions let you detect bit sequences that are counters or patterns identifying sub-commutated data. You can test data values and decide which sequence of instructions to follow based on the detected data value. Being able to test stream data and store the results for later use gives the decommutator the unique power to handle time-varying PCM formats. You can program the decommutator to process formats in which mainframe lengths, subcommutated sequence lengths, and subcommutated word positions all vary

dynamically, because the decommutator tracking is based on your programmed map of the format. With no bit counter, there is no maximum bit number between sync pattern repetitions, and if the data contains flags to direct the decommutator, a fixed number of bits is not  required. When a format contains only sub-commutated data synchronous to a single additional commutator, you can write the frame out unfolded, as though it were a very long mainframe of fixed sequence. This is not true if there are two or more subframes. The 1502V resolves the resulting asynchronism by providing separate tracking registers for

the mainframe and each of up to six subframes. Since each subframe is independently synchronized by patterns in the data, the decommutator is able to follow maps that vary for each subframe as well as for the mainframe. Each synchronizer can also transfer program control to a point in the map offset by the value of a data word, allowing you to decommutate subframes containing data identified by an ID word embedded in the data. Additional index registers and packet length counters make the

complete decommutation of embedded streams and packet telemetry in real-time a reality.

 

Features

 

Decommutates data streams to 32 MHz

• Frame-synchronizes and decommutates PCM streams from 0bps to 32Mbps.

Enlarged stored program space

• Supports up to 4 MBytes of program memory, allowing you to decommutate very complex, time-varying streams without having to reload the format in real-time.

• Assigns arbitrary ID tags in very large PCM formats (more than 131,000 unique data sources in the stream).

• Maintains program compatibility with previous decommutators while removing their program size limitations. Most of your existing 502VA software will run unchanged on the 1502V.

32-bit instruction word capability

• Assigns word properties and ID tags in a single instruction to speed program execution, and allows you to define word properties within a program region, rather than depending on program flow.

Non-segmented programs

• The 1502V instructions address the entire one-million-instruction program space, removing the previous 4k limitation. This increase removes limitations on program size to make programming larger formats easy.

• Supports up to 16-bit control and subframe ID words. For ID synchronized frames, this means that the major frame may contain as many as 65,536 minor frames. The subframe synchronizers in ID mode can collect up to 16 bits and, in recycle mode, up to 64 bits from non-contiguous locations in the bit stream.

• An enhanced repeat instruction allows a non-incrementing ID tag, permitting easy programming of sequences of a repeated

measurement.

Sixteen program flow control flags

• Control flags manage packet decommutation and data-directed format changes. The expanded capabilities now include set and reset instructions as well as data comparison tests. You can perform data comparisons and bit tests on 32-bit data words.

Plug-on modules

• Optional mezzanine cards support bit synchronization, IRIG time translation/generation, and format simulation.

Chapter 8 decommutation

• Eight address registers simplify decommutating IRIG-106 Chapter 8 embedded avionics data when you must calculate the output ID tag from data in the stream, a subframe register value, and a base value. This simplifies the complicated task of identifying a particular message based on its identifier in the stream and then sequencing through the message based upon its known structure.

Packet telemetry decommutation

• 16 presettable packet length counters control switching between programs when processing embedded, non-contiguous packet windows in the minor frame.

• 16-bit CRC check for packet telemetry stream error detection.

Current value table

• The CVT supports real-time display of decommutated PCM data in stand-alone systems that don’t require a data pre-processor or complex data distribution features.

Frame buffering system

• For applications requiring access to a PCM frame buffer, the 1502V has an on-board double buffer memory that stores minor

frames the host can access directly as a VME bus master.

Stream DMA

• The 1502V has a DMA channel that can transfer a stream of decommutated ID-tagged data to the host computer or other VME slave for recording or processing. Systems that do not need data pre-processing or other data distribution functions can implement the complete data system using just the 1502V and its supporting VME host computer. The 1502V does not rely on

the host computer to manage data identification, so the 1502V provides real-time data, remaining coherent to real-time, up to

the full data transfer bandwidth of the system, and is unaffected by host processor workload.

User-programmable output record formatting

• DMA or memory-mapped data transfers with user-selected record lengths.

• User-programmable message header, including time-of-day stamp, hardware status, record count, and up to three userspecified data words.

• Eleven user-selectable output formats, allowing 16 or 32-bit data words with or without ID tags.

 

System Software

GUI Setup and Operation Status for the 1502V is controlled via a single interface with drop down menus.

Technical Specs

INPUT

Sources

Program selectable, one of four inputs: three NRZ-L Data and
0Ί Clock inputs, one Internal Test Pattern input

Impedance

50 Ohm input impedance, TTL compatible

Bit Rate

Up to 32M bits per second

Polarity

Programmable, automatic polarity correction

Word Length

Programmable, 1 to 32 bit word length for each input

Word Orientation

Programmable, MSB/LSB orientation for each input word

Parity

Selectable leading, trailing or no parity checking for each word.

SYNCHRONIZATION

Mainframe Sync

Mainframe synchronization provides for programmable sync pattern and
mask, complement pattern recognition, and variable length frame decommutation.
The pattern may be up to 64 bits in length.

Subframe Sync

Six independent synchronizers are capable of decommutating sub-frames within
subframes. Subframes synchronize to fixed recycle patterns, complement frame sync
patterns, and various ID patterns. Both recycle and ID patterns may be assembled
from multiple word locations. Recycle patterns may be up to 64 bits in length.

ID Sync

Two types of ID synchronization are supported: JAM patterns of arbitrary values, and
incrementing or decrementing frame counters with limit checking. ID sync words may
be up to 10 bits in length.

Sync Strategy

Programmable Search-Check-Lock sync strategy, bit error tolerance, and bit slip
window provide reliable frame synchronization.

Asynchronous Formats

Subframe synchronizer may be programmed to decommutate embedded asynchronous
formats having unique frame sync patterns and format structures.

Format Switching

16 testable flags store the results of bit or word comparisons on the input stream to
control decommutation.

OUTPUT

Data

Data is 32 bits with programmable MSB/LSB output word justification, sign extension
or zero insertion for LSB output.

ID Tag

Unique ID tags may be assigned to each word; a total of 131,072 tags is possible.
The 32-bit ID word includes 17 bits of tag and two bits of status.

Frame Quality

Frame quality word is generated containing frame sync status for downstream data
validation.

2 Serial PCM Outputs

Two programmably controlled RS-422 compatible serial output channels are available
at the VME P2 connector

PHYSICAL

Format

Single Slot  6U VME

Cooling Requirements

30 Linear FPM

Power Requirements

+5VDC at 3 Amps

Temperature

Operating 0 to +40°C, non-operating –40 to +86°C

Relative Humidity

Up to 90% non-condensing

Shock

Operating 6G, Non-operating 25G

Vibration

Operating 0.5G, 5 to 2000Hz, Non-Operating 1.2G, 5 to 500Hz

specifications subject to change without notice

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